The present invention is directed, in general, to electronic devices and, more specifically, to a balancing circuit, method of operation thereof and a charge pump employing the circuit and method.
Phase locked loop (PLL) architectures are electronic circuits that control an oscillator to maintain a constant phase angle relative to a reference signal, such as a master clock signal. They are widely used in many digital applications, such as computer and communications systems, wherein derivative clock signals typically must be synchronized within the system. They may be used to accomplish functions such as coherent carrier tracking and threshold extension, bit synchronization and symbol synchronization.
PLL architectures typically employ a voltage controlled oscillator whose output frequency is proportional to an input voltage. This input voltage is often supplied by a capacitor wherein its voltage is increased or decreased by an incremental change to its charge. The capacitor provides a degree of filtering since its charge, and therefore its voltage, changes at a predetermined rate. A charge pump is used to provide a constant current of the required polarity to the capacitor. The charge pump receives a digital signal input from a feedback comparator circuit, which compares the phase of the output frequency to a reference input frequency. The comparator circuit directs an appropriate change to the charge pump to maintain a required phase of the output frequency to the reference frequency.
The digital signal input to the charge pump directs the polarity of its charge to the capacitor. To maintain a desired linearity of the output frequency, the values of the positive and negative charges supplied by the charge pump need to be within an appropriate tolerance of one another. Complimentary output drivers are typically employed to deliver the charging current from the charge pump. This dictates that the gain characteristics of the complementary output drivers should be within the appropriate tolerance of one another.
Large-area, complementary metal-oxide semiconductor (CMOS) devices are currently used as complementary output drivers in charge pump applications. These output devices are often biased in normal operation either at or above a rated breakdown voltage to provide an increased output voltage capability. When attempting to use a charge pump employing CMOS devices at supply voltages greater than rated voltage, reliability issues surface and problems begin to occur. In addition to gate oxide breakdown possibilities, the transistors may exhibit xe2x80x9chot carrierxe2x80x9d degradation of the threshold voltage under long term use. To avoid the latter problem, the devices may be fabricated with channel lengths that are eight to ten times a minimum channel width.
To exhibit a low conduction voltage characteristic, these transistors must also be designed with very wide gates to maintain a large enough width-to-length ratio. The resulting very large transistors exhibit a large parasitic capacitance, which must be charged during a turn-on of the device. These resulting large capacitor current pulses may be as much as ten times larger than the output currents, thereby creating noise on a substrate including the device similar to digital interference. This situation degrades the operation of radio frequency circuits on the same substrates. CMOS charge pumps, so constructed, exhibit difficulty meeting necessary pulse shape, matching and leakage requirements.
The use of complementary bipolar transistors as the complementary output drivers also exhibits several difficulties. The bias currents necessary to generate high speed output pulses using lateral bipolar transistors may be five to eight times greater than the required output current, thereby creating a substantial bias current drain. Vertical bipolar transistors allow acceptable switching speeds at higher supply voltages without the need for large bias currents thereby greatly reducing substrate noise and extensive bias current requirements. However, currently employable lateral and vertical bipolar transistors exhibit current gains that are very different between NPN and PNP polarities, sometimes by a ten-to-one margin. This condition currently discourages their use when appropriate positive and negative output current tolerance requirements are within a few percent of one another.
Accordingly, what is needed in the art is a circuit and method that facilitates the operation of complementary drivers that overcomes the deficiencies of the prior art.
To address the above-discussed deficiencies of the prior art, the present invention provides a balancing circuit and method of operation thereof for use with a circuit having first and second complementary drivers exhibiting different current gain characteristics. In one embodiment, the balancing circuit includes a sensing subcircuit that provides a correction signal indicating a first current gain characteristic of the first driver. The balancing circuit also includes a compensation subcircuit that generates a current gain compensation signal to the first driver to substantially match a second current gain characteristic of the second driver based on the correction signal.
In another aspect, the present invention provides a phase locked loop (PLL) circuit including a voltage controlled oscillator, coupled to a filter circuit, that receives a signal associated with a charging signal and provides an output signal having an output frequency. The PLL circuit also includes a comparator circuit that provides a comparison signal proportional to a phase difference between the output signal having the output frequency and an input reference signal having an input frequency. The PLL circuit still further includes a charge pump that provides the charging signal via first and second complementary drivers exhibiting different current gain characteristics. The charge pump has a balancing circuit including a sensing subcircuit that provides a correction signal indicating a first current gain characteristic of the first driver. The balancing circuit also includes a compensation subcircuit that generates a current gain compensation signal to the first driver to substantially match a second current gain characteristic of the second driver based on the correction signal.
The foregoing has outlined, rather broadly, preferred and alternative features of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiment as a basis for designing or modifying other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form.